Last week, the U.S. Court of Appeals for the Federal Circuit issued a precedential opinion in Netlist, Inc. v. Micron Technology, Inc., No. 2024-1707 (Sept. 2, 2026), affirming the Patent Trial and Appeal Board’s final written decision that all challenged claims of U.S. Patent No. 10,949,339 (the “’339 Patent”) are unpatentable as obvious.
Netlist’s ’339 Patent relates to computer memory systems using buffers between a memory controller and DRAM devices. The buffers have data paths that are generally disabled to isolate the DRAM devices but are selectively enabled during read or write operations to drive the data signal.
Micron and Samsung Electronics Co., Ltd. (“Samsung”) petitioned for inter partes review, arguing claims 1-35 of the ’339 Patent were unpatentable as obvious over the combination of U.S. Patent Application Publication No. 2006/0277355 (“Ellsberry”) and U.S. Patent No. 7,024,518 (“Halbert”). Representative claim 1 requires that a “data path” through the buffer is “enabled” at a certain time (“in accordance with a latency parameter”) for a certain duration (a “first time period”) so that a memory controller can drive write data through the buffer to the DRAM device.
The Board found all challenged claims obvious. Netlist appealed, arguing the Board erred by (1) determining Ellsberry teaches data paths enabled “in accordance with a latency parameter” and “enabl[ing]” a “data path,” and (2) violating the APA.
The Federal Circuit affirmed. On the latency parameter, the Court found substantial evidence supported the Board’s determination. Specifically, Ellsberry disclosed storing “Posted CAS_n” in the memory bank switch. The Court also rejected Netlist’s assertion that the Board improperly relied on Netlist’s U.S. Patent No. 7,532,537, which was not part of Samsung’s petition, noting any error was harmless because the Board found that Ellsberry alone teaches adding one clock cycle of latency to account for the buffers.
On “enabl[ing]” a “data path,” Netlist claimed that Ellsberry directly enables and disables memory banks outside the buffer rather than connecting and disconnecting data paths within it. The Court ruled substantial evidence supported the Board’s determination that Ellsberry’s Ports A and B are components within the switch ASIC and that enabling the ports constitutes enabling data paths. The Court also noted the Board’s alternative finding that the Ellsberry and Halbert combination teaches this limitation.
Finally, the Court rejected Netlist’s APA arguments, claiming that the Board adequately addressed Netlist’s arguments and that Netlist did not develop its other contentions on appeal.
